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已通过RTL 设计与集成AUD-9C4D00E3E7

RTL 代码生成助手

把已评审的架构说明、接口表、寄存器表和时序约束转成可综合 Verilog/SystemVerilog，并同步产出追踪表、Lint 检查清单和验证交接说明。

查看 Skill 详情
94
Benchmark
96%
通过率
7
检查项
low
风险等级
自动检查
SKILL.md format and section validation
通过

skills/rtl-code-generator/SKILL.md

  • Required frontmatter and sections are present.
Hardcoded secret scan
通过

skills/rtl-code-generator

  • No private key, cloud key, token, or long generic secret matched.
High-risk behavior scan
通过

skills/rtl-code-generator

  • No recursive deletion, cloud metadata access, encoded shell, or unreviewed transfer matched.
Declared dependency inventory
通过

skills/rtl-code-generator

  • No runtime dependency manifest is included in this Skill package.
Sandbox dry-run readiness
通过

skills/rtl-code-generator

  • Package is documentation/reference only, so runtime sandbox is marked as dry-run ready.
Benchmark evidence completeness
通过

skills/rtl-code-generator/SKILL.md

  • Score 94, level A, pass rate 96%.
Human review gate
通过

skills/rtl-code-generator/SKILL.md

  • Status is official.
Benchmark 套件
Format and metadata fixtures10/10

content/audit/evidence/rtl-code-generator/bm-fmt.json

IC workflow scenario cases24/25

content/audit/evidence/rtl-code-generator/bm-scenario.json

Safety and guardrail cases10/10

content/audit/evidence/rtl-code-generator/bm-safety.json

Regression and replay cases4/5

content/audit/evidence/rtl-code-generator/bm-regression.json

包盘点
Package hash
sha256:rtl11094
Files
2
Executables
0
Decision
publishable